Many applications performed on microprocessors or digital signal processors require repeating computational steps for a predetermined number of repetitions, or until a predetermined condition is met. Repeating a step or sequence of steps is referred to as a loop. The number of time a loop is executed is tracked by a loop counter that counts the number of time the computation in the loop has been performed.
When loops are nested, the inner loop in the case of two nested loops, or the inner loops in the case of more than two nested loops, is/are repeated until the outermost loop has executed a predetermined number of times. Each time an inner loop counts through its associated predetermined number of count times, an outer loop counter is updated, such as being decremented, the inner loop counter is reset to a predetermined value, and the inner loop repeatedly executed the number of times of the predetermined value.
Software techniques have typically been used to reload loop counters in microprocessors. While only a few instruction cycles are required for each software counter reload operation, a detrimental impact on the processor performance occurs. Implementation of loop counter reloading in hardware can obviate the detrimental impact on processor performance.